The semiconductor has been developed for four decades from the birth of the first semiconductor device. For performing more complicate operations with higher speed, more and more devices and connections are formed within a circuit. The density of semiconductor chips are raised to include more devices and functions in a single chip. In the integrated circuits, a great number of devices and connections are fabricated on a single chip. Various kinds of devices like transistors, resistors, and capacitors are formed together. Each device must operate with the good connections to provide interaction between each other for completing the functionality, especially under the higher and higher packing density of the integrated circuits.
Connections must be formed between these densely arranged devices for finishing a circuit to perform operations. In the semiconductor manufacturing process, metallization is a process for forming connections between devices. With more and more devices on a chip under high integrity, early stage single layer metallization process had been improved to form multiple layer of connections. Two layers, three layers, or even four layers of connections are formed in present applications. With the sub-micrometer or even smaller devices, the metallization process is challenged with forming narrower conductive lines with compromising resistance. More layers of connections must be formed with low misalignment and good yield.
For fabricating high density devices like ULSI (ultra-large scale integration) devices, metallization with small pitch and multilevel-structure become necessary for providing high packing density with reliable functionality. In the metallization process, the planarization process is a vital role in providing accurately defined conductive paths and densely packed connections. The demand for more levels of metal wiring in the integrated circuits of complexity has greatly raised the need for the global planarity and dielectric characteristics of inter-metal dielectric (IMD) layers.
Without limiting the scope and the spirit of the present invention, a typical metallization process on forming an inter-metal dielectric layer is illustrated. Referring to FIG. 1, a substrate 10, generally having devices like transistors and/or capacitors formed thereon, is provided for making interconnections between devices. A metal layer is formed on the substrate 10 and is then patterned to define metal wiring or interconnection structures such as 12a and 12b illustrated in the figure. A liner oxide 14 is formed to cover over the interconnection structures 12a and 12b.
Following the liner oxide layer 14, a first dielectric layer 16 covers over the liner oxide layer 14. Since the pitch between the interconnection structures 12a and 12b are tight for present stage high density circuits, a dielectric layer with very low dielectric constant (K), such as a low-K organic layer, is employed as the first dielectric layer 16, in order to reduce the RC constant between the interconnection structures 12a and 12b and between metal layers of different levels. A second dielectric layer 18 then covers over the first dielectric layer 16 to serve as a top layer of the composite inter-metal dielectric layer. The second dielectric layer 18 is generally a silicon oxide layer.
In the typical metallization process, a planarization process is performed after the formation of the second dielectric layer 18, in order to improve the topography of the composite inter-metal dielectric layer and provide a planar surface for forming next layer of conductive wires accurately. The second dielectric layer 18 is polished to leave a portion of the second dielectric layer 18 to cover over the first dielectric layer 16, such as the left portion 18a of the second dielectric layer 18 illustrated in FIG. 2. As an example, the left portion 18a is about a thousand angstroms to several thousand angstroms. In the conventional planarization processes, a chemical-mechanical polish (CMP) is applied to planarize the second dielectric layer.
However, during the planarization of the second dielectric layer 18, the polishing process is difficult to control. Since the whole polishing process is carried out and also stop on the same material of silicon oxide, no endpoint for the polishing process can be clearly defined. Under the same-layer polishing without identified endpoint or stop layer, the uniformity of the polishing process, including within-wafer uniformity and wafer-to-wafer uniformity, can be greatly damaged. Some of the regions on the wafer may be over-polished to damage the insulation characteristics and some of the regions may be under-polished to reduce the essential planarity for accurately defining metal wiring. The yield and reliability of the products are also decreased.
Furthermore, the conventional chemical-mechanical polish process, under the mechanical polishing of the abrasive particles, has the problem of scratches on the polished surface. Therefore, as shown in FIG. 2, the polishing step will result in a plurality of scratch defects on the remained second dielectric layer 18a. The scratch defects can be recessed regions, shallow channels, or small holes. In the plug-formation process, the deposition and etch-back of a conductive layer to form a plug 20 will leave some conductive material in the scratch defects, thus form some micro wirings such as 20a and 20b. The present of the micro wirings 20a and 20b, which might have conductive connections with plugs or conductive paths, will lead to the formation of undesired contacts, leakage paths, or short connections between individual paths and damage the functionality of integrated circuits.